1. Field of the Invention
This invention relates generally to the area of digital data processing equipment, and, in particular, to a direct memory access controller.
2. Description of the Related Art
In a digital data processing system, the central processing unit (CPU) generally operates at a very fast cycle rate in comparison to the data transfer rate of the input/output device of the system. Such input/output devices have frequent need to transfer data to and from a memory unit in the system. The CPU also needs to access such memory unit. To preserve the integrity of the information stored in the memory unit, such information cannot be accessed simultaneously by the CPU and the input/output devices.
Systems are known in which the CPU itself services all transfers between the input/output devices and the memory unit. However, in systems with many input/output devices demanding I/O services, the CPU performance is degraded.
Systems are also known in which the technique referred to as direct memory access (DMA) is employed. Using direct memory access, information can be directly transferred between the input/output devices and the memory unit with only minimal involvement by the CPU. Typically, an input/output device makes an I/O request to a corresponding input/output controller, which request is honored if it is of sufficient priority. Then that input/output device controls the system bus until the DMA transfer has been completed or until a higher priority request is made by another input/output device.
Some prior DMA systems provided only a single DMA register set for use by a large number of input/output devices, which register set had to be loaded for each DMA transfer. In other DMA systems, each input/output controller has its own set of DMA address, count, and control registers, which is expensive to implement.
The present invention represents an improvement over known DMA systems in that it provides for interleaved DMA operations of a number of I/O controllers. This is accomplished through the use of short bursts of DMA activity by each I/O controller. Between bursts, the I/O controllers are polled in a round robin manner to determine if any of them have active DMA requests. Thus all I/O controllers share the system bus in a time-division multiplexed fashion which provides sufficient bandwidth to each I/O controller to keep up with its real-time demands.
A number of DMA channels are assigned to each I/O controller. Each DMA channel has its own set of DMA registers, so that an I/O operation can be in progress on each input/output device in the system concurrently. The operating system software sets up a DMA channel when an I/O device initiates a request, but the system software then remains uninvolved until the I/O device requires termination of the I/O interrupt request.
Known data processing systems utilize more than one memory unit. The data processing system of the present invention provides one memory unit for the central processing unit (CPU) for storing data and instructions relating to operating system software and applications software, and a second memory unit for an I/O processor, referred to as the Master Input Output Processor (MIOP), for storing data and instructions relating to transfers of information between input/output devices and the system.
The present invention also utilizes two system busses. One services the CPU and the other services the MIOP. The present invention represents a further improvement over known multi-processor data processing systems, in that it allows for DMA bi-directional transfers between any input/output device and either system memory unit. It also provides for DMA bi-directional transfers between the system memory units, as well as for block moves within either system memory unit.